Thoughts on Programming

August 8, 2011

Unix “make” command

Filed under: Linux — shadiyya @ 6:27 pm

This post is a short introduction to the Unix make utility.The make utility is a software engineering tool for managing and maintaining computer programs. Make provides most help when the program consists of many component files. As the number of files in the program increases so to does the compile time, complexity of compilation command and the likelihood of human error when entering command lines, i.e. typos and missing file names.

By creating a descriptor file containing dependency rules, macros and suffix rules, you can instruct make to automatically rebuild your program whenever one of the program’s component files is modified. makeis smart enough to only recompile the files that were affected by changes thus saving compile time.

If you run:

make

this program will look for a file named ‘makefile’ in your directory, and then execute it.
If you have several makefiles, then you can execute them with the command:

make -f MyMakefile

Simple Example

This is an example descriptor file to build an executable file called prog1. It requires the source files file1.c, file2.c, and file3.c. An include file, mydefs.h, is required by files file1.c and file2.c. If you wanted to compile this file from the command line using c the command would be

% cc -o prog1 file1.c file2.c file3.c

This command line is rather long to be entered many times as a program is developed and is prone to typing errors. A descriptor file could run the same command better by using the simple command

% make prog1

or if prog1is the first target defined in the descriptor file

% make

This first example descriptor file is much longer than necessary but is useful for describing what is going on.

prog1 : file1.o file2.o file3.o

cc -o prog1 file1.o file2.o file3.o

file1.o : file1.c mydefs.h

cc -c file1.c

file2.o : file2.c mydefs.h

cc -c file2.c

file3.o : file3.c

cc -c file3.c

clean : rm file1.o file2.o file3.o

Let’s go through the example to see what make does by executing with the command make prog1and assuming the program has never been compiled.
makefinds the target prog1 and sees that it depends on the object files file1.o file2.o file3.o

makenext looks to see if any of the three object files are listed as targets. They are so make looks at each target to see what it depends on. make sees that file1.o depends on the files file1.cc and mydefs.h

Now make looks to see if either of these files are listed as targets and since they aren’t it executes the commands given in file1.o’s rule and compiles file1.cc to get the object file.

make looks at the targets file2.o and file3.o and compiles these object files in a similar fashion.

make now has all the object files required to make prog1 and does so by executing the commands in its rule.

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